mSoC™ Power Management: Redundancy, Isolation, and Graceful Degradation

SANTA CLARA, CA — This demonstration presents the mSoC power management philosophy for safety critical autonomy. The system is built from a tiled fabric of chiplets surrounded by LPDDR memory, where every chiplet is treated as an independently controllable safety island. Power delivery is redundant by design: each tile is fed by two independent regulation lanes, VRM A and VRM B, backed by separate distribution rails Vcc0 and Vcc1, so single faults do not immediately translate into loss of compute.

When stability cannot be guaranteed, the architecture prefers deterministic states: tiles are isolated and placed into a defined safe condition, preventing partial brownout behavior that can corrupt memory or create intermittent failures. Monitoring is continuous and collective. An odd number of peer chiplets supervise each tile, measuring incoming voltage and current, sharing telemetry, and voting to keep a tile online, throttle it, or power gate it. This distributed authority stops cascading failures early and enables controlled recovery back to standby before re admission.

The demo also links power integrity to fabric integrity by visualizing how interconnect health and communication continuity must track rail stability, especially when transitioning between Level 3 and Level 4 autonomy policies. It highlights reliability as a prerequisite for scalable deployment.